Tb/and

From HDLBits

tb/tb1Previous
Nexttb/tb2

You are given the following AND gate you wish to test:

module andgate (
    input [1:0] in,
    output out
);

Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram:

Module Declaration

module top_module();

Write your solution here

Upload a source file...