Exams/ece241 2013 q7

From HDLBits

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

JKQ
00Qold
010
101
11~Qold

Module Declaration

module top_module (
    input clk,
    input j,
    input k,
    output Q); 

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