Exams/m2014 q4a

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Nextexams/m2014_q4b

Implement the following circuit:

Note that this is a latch, so a Quartus warning about having inferred a latch is expected.

Module Declaration

module top_module (
    input d, 
    input ena,
    output q);

Hint...

• Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
• However, they are still sequential elements, so should use non-blocking assignments.
• A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.

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module top_module( ); endmodule

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