Exams/2014 q3bfsm

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Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.

Present state
y[2:0]
Next state Y[2:0]Output z
x=0x=1
0000000010
0010011000
0100100010
0110010101
1000111001

Module Declaration

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);

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