Fsm2s

From HDLBits

fsm2Previous

This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

This exercise is the same as fsm2, but using synchronous reset.

Module Declaration

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); 
//  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
    end

    always @(posedge clk) begin
        // State flip-flops with synchronous reset
    end

    // Output logic
    // assign out = (state == ...);

Yes, there are ways to do this other than writing an FSM. But that wasn't the point of this exercise.
This is a JK flip-flop.

Write your solution here

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module top_module(
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    input clk,
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    input reset,    // Synchronous reset to OFF
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    input j,
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    input k,
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    output out); //  
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    parameter OFF=0, ON=1; 
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    reg state, next_state;
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    always @(*) begin
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        // State transition logic
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    end
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    always @(posedge clk) begin
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        // State flip-flops with synchronous reset
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    end
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    // Output logic
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    // assign out = (state == ...);
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endmodule
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