Fsm2s

From HDLBits

fsm2Previous
Nextfsm3comb

This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

This exercise is the same as fsm2, but using synchronous reset.

Module Declaration

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); 
//  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
    end

    always @(posedge clk) begin
        // State flip-flops with synchronous reset
    end

    // Output logic
    // assign out = (state == ...);

Yes, there are ways to do this other than writing an FSM. But that wasn't the point of this exercise.
This is a JK flip-flop.

Write your solution here

​x
 
1
module top_module(
2
    input clk,
3
    input reset,    // Synchronous reset to OFF
4
    input j,
5
    input k,
6
    output out); //
7
​
8
    parameter OFF=0, ON=1;
9
    reg state, next_state;
10
​
11
    always @(*) begin
12
        // State transition logic
13
    end
14
​
15
    always @(posedge clk) begin
16
        // State flip-flops with synchronous reset
17
    end
18
​
19
    // Output logic
20
    // assign out = (state == ...);
21
​
22
endmodule
23
​
Upload a source file...

Retrieved from "https://hdlbits.01xz.net/mw/index.php?title=Fsm2s&oldid=1651"