Vectorr

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Given an 8-bit input vector [7:0], reverse its bit ordering.

See also: Reversing a longer vector.

Module Declaration

module top_module( 
    input [7:0] in,
    output [7:0] out
);









  • assign out[7:0] = in[0:7]; does not work because Verilog does not allow vector bit ordering to be flipped.
    • 

  • The concatenation operator may save a bit of coding, allowing for 1 assign statement instead of 8.




Write your solution here


		






​x
 
1
module top_module( 
2
    input [7:0] in,
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    output [7:0] out
4
);
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​
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endmodule
7
​

  
  
  
  





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