Vector100r

gates100Previous

Nextpopcount255

Given a 100-bit input vector [99:0], reverse its bit ordering.

Module Declaration

module top_module( 
    input [99:0] in,
    output [99:0] out
);

Hint...

A for loop (in a combinational always block or generate block) would be useful here. I would prefer a combinational always block in this case because module instantiations (which require generate blocks) aren't needed.

Write your solution here

[Load a previous submission]Load

module top_module( ); endmodule

Upload a source file...

Or upload a file

Verilog source:

Show solution

Solution

Loading...

• always_if2
• always_case
• always_case2
• always_casez
• always_nolatches
• conditional
• reduction
• gates100 ·

vector100r

• · popcount255
• adder100i
• bcdadd100
• exams/m2014_q4h
• exams/m2014_q4i
• exams/m2014_q4e
• exams/m2014_q4f
• exams/m2014_q4g

gates100Previous

Nextpopcount255