Tb/tb2
From HDLBits
The waveform below sets clk, in, and s:
Module q7 has the following declaration:
module q7 (
input clk,
input in,
input [2:0] s,
output out
);
Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.
Module Declaration
module top_module();