Tb/tb1
From HDLBits
Create a Verilog testbench that will produce the following waveform for outputs A and B:
Module Declaration
module top_module ( output reg A, output reg B );
Create a Verilog testbench that will produce the following waveform for outputs A and B:
module top_module ( output reg A, output reg B );
//
// generate input patterns here
initial begin
end