Tb/tb1

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Create a Verilog testbench that will produce the following waveform for outputs A and B:

05101520253035404550AB

Module Declaration

module top_module ( output reg A, output reg B );
//

    // generate input patterns here
    initial begin

    end

Write your solution here

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module top_module ( output reg A, output reg B );//
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    // generate input patterns here
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    initial begin
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    end
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endmodule
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