Tb/tb1

From HDLBits

tb/clockPrevious
Nexttb/and

Create a Verilog testbench that will produce the following waveform for outputs A and B:

05101520253035404550AB

Module Declaration

module top_module ( output reg A, output reg B );
//

    // generate input patterns here
    initial begin

    end

Write your solution here

​x
 
1
module top_module ( output reg A, output reg B );//
2
​
3
    // generate input patterns here
4
    initial begin
5
​
6
    end
7
​
8
endmodule
9
​
Upload a source file...

Retrieved from "https://hdlbits.01xz.net/mw/index.php?title=Tb/tb1&oldid=1559"