Tb/clock
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You are provided a module with the following declaration:
module dut ( input clk ) ;
Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.
Module Declaration
module top_module ( );
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