Exams/m2014 q4b

From HDLBits

Implement the following circuit:

Module Declaration

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);

Write your solution here

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module top_module (
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    input clk,
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    input d, 
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    input ar,   // asynchronous reset
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    output q);
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endmodule
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