Exams/ece241 2013 q8
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fsm_hdlcPrevious
Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
Module Declaration
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z );
fsm_hdlcPrevious