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Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

Module Declaration

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q

Resetting a register to '1' is sometimes called "preset"

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