Dff8ar

From HDLBits

dff8pPrevious
Nextdff16e

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

Module Declaration

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);






The only difference in code between synchronous and asynchronous reset flip-flops is in the sensitivity list.






Write your solution here


		







  
  
  
  





Upload a source file... 






























Retrieved from "https://hdlbits.01xz.net/mw/index.php?title=Dff8ar&oldid=1768"