Countslow

From HDLBits

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

clkresetslowenaq0123401

Module Declaration

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);






This is a regular decade counter with an enable control signal






Write your solution here


		






​x
 
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module top_module (
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    input clk,
3
    input slowena,
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    input reset,
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    output [3:0] q);
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​
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endmodule
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​

  
  
  
  





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