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This three-input NAND gate doesn't work. Fix the bug(s).

You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e );

Module Declaration

module top_module (input a, input b, input c, output out);

//

    andgate inst1 ( a, b, c, out );

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module top_module( ); endmodule

​x

 

1

module top_module (input a, input b, input c, output out);//

2

​

3

    andgate inst1 ( a, b, c, out );

4

​

5

endmodule

6

​

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bugs_nand3

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