Fsm serialdata

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See also: Serial receiver

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

Some timing diagrams

Error-free:

Module Declaration

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); 

//

    // Use FSM from Fsm_serial

    // New: Datapath to latch input bits.

Hint...

The serial bitstream needs to be shifted in one bit at a time, then read out in parallel.

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module top_module( ); endmodule

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• lemmings1
• lemmings2
• lemmings3
• lemmings4
• fsm_onehot
• fsm_ps2
• fsm_ps2data
• fsm_serial ·

fsm_serialdata

• · fsm_serialdp
• fsm_hdlc
• exams/ece241_2013_q8
• exams/ece241_2014_q5a
• exams/ece241_2014_q5b
• exams/2014_q3fsm
• exams/2014_q3bfsm
• exams/2014_q3c

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