Exams/ece241 2014 q4

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Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.


Module Declaration

module top_module (
    input clk,
    input x,
    output z
); 






Be careful with the reset state. Ensure that each D flip-flop's Q output is really the inverse of its Q output, even before the first clock edge of the simulation.






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