Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in, sel=1 selects bits in, sel=2 selects bits in, etc.
Expected solution length: Around 1 line.
module top_module( input [255:0] in, input [7:0] sel, output out );
- With this many options, a case statement isn't so useful.
- Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.
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