Fsm serialdata

From HDLBits


See also: Serial receiver

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

Some timing diagrams


Module Declaration

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done

    // Use FSM from Fsm_serial

    // New: Datapath to latch input bits.

The serial bitstream needs to be shifted in one bit at a time, then read out in parallel.

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