Exams/review2015 fsmseq

From HDLBits

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

Module Declaration

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);

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