Consider the state machine shown below, which has one input w and one output z.
Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flop y.
Implement just the next-state logic for y. (This is much more a FSM question than a Verilog coding question. Oh well.)
module top_module ( input [3:1] y, input w, output Y2);
Write your solution here