Exams/m2014 q6

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Consider the state machine shown below, which has one input w and one output z.

Exams m2014q6.png

Implement the state machine. (This part wasn't on the midterm, but coding up FSMs is good practice).

Module Declaration

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);

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