Exams/2012 q2fsm

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Consider the state diagram shown below.

Exams 2012q2.png

Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM output, which is called z, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.

Module Declaration

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z

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