Consider the state diagram shown below.
Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM output, which is called z, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.
module top_module ( input clk, input reset, // Synchronous active-high reset input w, output z );
Write your solution here