From HDLBits


Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

Module Declaration

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q

The only difference in code between synchronous and asynchronous reset flip-flops is in the sensitivity list.

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